
Obj/FWlib_apt32f172_adc.o:     file format elf32-csky-little


Disassembly of section .text:

00000000 <ADC12_RESET_VALUE>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/  
void ADC12_RESET_VALUE(void)
{
	 ADC0->ECR	=	ADC_ECR_RST;     				/**< ECR  reset value  */
   0:	107a      	lrw      	r3, 0	// 68 <ADC12_RESET_VALUE+0x68>
   2:	3200      	movi      	r2, 0
   4:	9360      	ld.w      	r3, (r3, 0)
   6:	b340      	st.w      	r2, (r3, 0)
	 ADC0->DCR	=	ADC_DCR_RST;                  	/**< DCR  reset value  */
   8:	b341      	st.w      	r2, (r3, 0x4)
	 ADC0->PMSR	= 	ADC_PMSR_RST;       		  	/**< PMSR reset value  */
   a:	b342      	st.w      	r2, (r3, 0x8)
	 ADC0->CR	=	ADC_CR_RST;             		/**< CR   reset value  */
   c:	1058      	lrw      	r2, 0x80000040	// 6c <ADC12_RESET_VALUE+0x6c>
   e:	b344      	st.w      	r2, (r3, 0x10)
	 ADC0->MR	=   ADC_MR_RST;                  	/**< MR   reset value  */
  10:	3200      	movi      	r2, 0
  12:	b345      	st.w      	r2, (r3, 0x14)
	 ADC0->CSR	=   ADC_CSR_RST;                  	/**< CSR  reset value  */
  14:	b347      	st.w      	r2, (r3, 0x1c)
	 ADC0->SR 	=	ADC_SR_RST;                   	/**< SR   reset value  */
  16:	b348      	st.w      	r2, (r3, 0x20)
	 ADC0->IER 	=	ADC_IER_RST;                	/**< IER  reset value  */
  18:	b349      	st.w      	r2, (r3, 0x24)
	 ADC0->IDR 	=	ADC_IDR_RST;              		/**< IDR  reset value  */
  1a:	b34a      	st.w      	r2, (r3, 0x28)
	 ADC0->IMR  	=	ADC_IMR_RST;               		/**< IMR  reset value  */
  1c:	b34b      	st.w      	r2, (r3, 0x2c)
	 ADC0->SEQ[0]=	ADC_SEQx_RST;             		/**< SEQ0  reset value */
  1e:	b34c      	st.w      	r2, (r3, 0x30)
	 ADC0->SEQ[1]=	ADC_SEQx_RST;             		/**< SEQ1  reset value */
  20:	b34d      	st.w      	r2, (r3, 0x34)
	 ADC0->SEQ[2]=	ADC_SEQx_RST;             		/**< SEQ2  reset value */
  22:	b34e      	st.w      	r2, (r3, 0x38)
	 ADC0->SEQ[3]=	ADC_SEQx_RST;             		/**< SEQ3  reset value */
  24:	b34f      	st.w      	r2, (r3, 0x3c)
	 ADC0->SEQ[4]=	ADC_SEQx_RST;             		/**< SEQ4  reset value */
  26:	b350      	st.w      	r2, (r3, 0x40)
	 ADC0->SEQ[5]=	ADC_SEQx_RST;             		/**< SEQ5  reset value */
  28:	b351      	st.w      	r2, (r3, 0x44)
	 ADC0->SEQ[6]=	ADC_SEQx_RST;             		/**< SEQ6  reset value */
  2a:	b352      	st.w      	r2, (r3, 0x48)
	 ADC0->SEQ[7]=	ADC_SEQx_RST;             		/**< SEQ7  reset value */
  2c:	b353      	st.w      	r2, (r3, 0x4c)
	 ADC0->SEQ[8]=	ADC_SEQx_RST;             		/**< SEQ8  reset value */
  2e:	b354      	st.w      	r2, (r3, 0x50)
	 ADC0->SEQ[9]=	ADC_SEQx_RST;             		/**< SEQ9  reset value */
  30:	b355      	st.w      	r2, (r3, 0x54)
	 ADC0->SEQ[10]=	ADC_SEQx_RST;             		/**< SEQ10  reset value */
  32:	b356      	st.w      	r2, (r3, 0x58)
	 ADC0->SEQ[11]=	ADC_SEQx_RST;             		/**< SEQ11  reset value */
  34:	b357      	st.w      	r2, (r3, 0x5c)
	 ADC0->SEQ[12]=	ADC_SEQx_RST;             		/**< SEQ12  reset value */
  36:	b358      	st.w      	r2, (r3, 0x60)
	 ADC0->SEQ[13]=	ADC_SEQx_RST;             		/**< SEQ13  reset value */
  38:	b359      	st.w      	r2, (r3, 0x64)
	 ADC0->SEQ[14]=	ADC_SEQx_RST;             		/**< SEQ14  reset value */
  3a:	b35a      	st.w      	r2, (r3, 0x68)
	 ADC0->SEQ[15]=	ADC_SEQx_RST;             		/**< SEQ15  reset value */
  3c:	b35b      	st.w      	r2, (r3, 0x6c)
	 ADC0->DR[0]  =	ADC_DR_RST;                		/**< DR   reset value  */
  3e:	23ff      	addi      	r3, 256
  40:	b340      	st.w      	r2, (r3, 0)
	 ADC0->DR[1]  =	ADC_DR_RST;                		/**< DR   reset value  */
  42:	b341      	st.w      	r2, (r3, 0x4)
	 ADC0->DR[2]  =	ADC_DR_RST;                		/**< DR   reset value  */
  44:	b342      	st.w      	r2, (r3, 0x8)
	 ADC0->DR[3]  =	ADC_DR_RST;                		/**< DR   reset value  */
  46:	b343      	st.w      	r2, (r3, 0xc)
	 ADC0->DR[4]  =	ADC_DR_RST;                		/**< DR   reset value  */
  48:	b344      	st.w      	r2, (r3, 0x10)
	 ADC0->DR[5]  =	ADC_DR_RST;                		/**< DR   reset value  */
  4a:	b345      	st.w      	r2, (r3, 0x14)
	 ADC0->DR[6]  =	ADC_DR_RST;                		/**< DR   reset value  */
  4c:	b346      	st.w      	r2, (r3, 0x18)
	 ADC0->DR[7]  =	ADC_DR_RST;                		/**< DR   reset value  */
  4e:	b347      	st.w      	r2, (r3, 0x1c)
	 ADC0->DR[8]  =	ADC_DR_RST;                		/**< DR   reset value  */
  50:	b348      	st.w      	r2, (r3, 0x20)
	 ADC0->DR[9]  =	ADC_DR_RST;                		/**< DR   reset value  */
  52:	b349      	st.w      	r2, (r3, 0x24)
	 ADC0->DR[10]  =	ADC_DR_RST;                		/**< DR   reset value  */
  54:	b34a      	st.w      	r2, (r3, 0x28)
	 ADC0->DR[11]  =	ADC_DR_RST;                		/**< DR   reset value  */
  56:	b34b      	st.w      	r2, (r3, 0x2c)
	 ADC0->DR[12]  =	ADC_DR_RST;                		/**< DR   reset value  */
  58:	b34c      	st.w      	r2, (r3, 0x30)
	 ADC0->DR[13]  =	ADC_DR_RST;                		/**< DR   reset value  */
  5a:	b34d      	st.w      	r2, (r3, 0x34)
	 ADC0->DR[14]  =	ADC_DR_RST;                		/**< DR   reset value  */
  5c:	b34e      	st.w      	r2, (r3, 0x38)
	 ADC0->DR[15]  =	ADC_DR_RST;                		/**< DR   reset value  */
  5e:	b34f      	st.w      	r2, (r3, 0x3c)
	 ADC0->CMP0   =	ADC_CMP0_RST;               	/**< CMP1 reset value  */
  60:	b350      	st.w      	r2, (r3, 0x40)
	 ADC0->CMP1   =	ADC_CMP1_RST;                	/**< CMP2 reset value  */
  62:	b351      	st.w      	r2, (r3, 0x44)
}  
  64:	783c      	rts
  66:	0000      	bkpt
  68:	00000000 	.long	0x00000000
  6c:	80000040 	.long	0x80000040

00000070 <ADC12_read_IPIDCODE>:
//EntryParameter:NONE
//ReturnValue:ADC IPIDCODE
/*************************************************************/  
U32_T ADC12_read_IPIDCODE(void)
{
	return (ADC0->PMSR&ADC12_IPIDCODE_MASK);
  70:	1366      	lrw      	r3, 0	// 208 <ADC12_Configure_VREF_FVR+0x2>
  72:	9360      	ld.w      	r3, (r3, 0)
  74:	9302      	ld.w      	r0, (r3, 0x8)
  76:	1366      	lrw      	r3, 0x3fffffff	// 20c <ADC12_Configure_VREF_FVR+0x6>
  78:	2b0e      	subi      	r3, 15
  7a:	680c      	and      	r0, r3
}  
  7c:	783c      	rts

0000007e <ADC12_Control>:
//ReturnValue:NONE
/*************************************************************/  
  //control:ADC enable/disable ,start/stop,swrst
void ADC12_Control(ADC12_Control_TypeDef ADC12_Control_x )
{
	ADC0->CR |= ADC12_Control_x;							// 
  7e:	1363      	lrw      	r3, 0	// 208 <ADC12_Configure_VREF_FVR+0x2>
  80:	9340      	ld.w      	r2, (r3, 0)
  82:	9264      	ld.w      	r3, (r2, 0x10)
  84:	6c0c      	or      	r0, r3
  86:	b204      	st.w      	r0, (r2, 0x10)
}
  88:	783c      	rts

0000008a <ADC12_CMD.part.0>:
//ADC12 ENABLE
//EntryParameter:NewState
//NewState:ENABLE , DISABLE
//ReturnValue:NONE
/*************************************************************/ 
void ADC12_CMD(FunctionalStatus NewState)
  8a:	14d0      	push      	r15
{
	if (NewState != DISABLE)
	{
		ADC12_Control(ADC12_ADCEN);						//ADC12 ENABLE
  8c:	3002      	movi      	r0, 2
  8e:	e0000000 	bsr      	0	// 7e <ADC12_Control>
		while(!(ADC0->SR &ADC12_ADCENS));
  92:	127e      	lrw      	r3, 0	// 208 <ADC12_Configure_VREF_FVR+0x2>
  94:	3280      	movi      	r2, 128
  96:	9320      	ld.w      	r1, (r3, 0)
  98:	4241      	lsli      	r2, r2, 1
  9a:	9168      	ld.w      	r3, (r1, 0x20)
  9c:	68c8      	and      	r3, r2
  9e:	3b40      	cmpnei      	r3, 0
  a0:	0ffd      	bf      	0x9a	// 9a <ADC12_CMD.part.0+0x10>
	else
	{
		ADC12_Control(ADC12_ADCDIS);					//ADC12 DISABLE
		while(ADC0->SR&ADC12_ADCENS);
	}
}
  a2:	1490      	pop      	r15

000000a4 <ADC12_ConfigInterrupt_CMD>:
	if (NewState != DISABLE)
  a4:	3940      	cmpnei      	r1, 0
  a6:	1279      	lrw      	r3, 0	// 208 <ADC12_Configure_VREF_FVR+0x2>
  a8:	0c06      	bf      	0xb4	// b4 <ADC12_ConfigInterrupt_CMD+0x10>
		ADC0->IER  |= ADC_IMR_X;						//SET
  aa:	9340      	ld.w      	r2, (r3, 0)
  ac:	9269      	ld.w      	r3, (r2, 0x24)
  ae:	6c0c      	or      	r0, r3
  b0:	b209      	st.w      	r0, (r2, 0x24)
} 
  b2:	783c      	rts
		ADC0->IDR  |= ADC_IMR_X;						//CLR
  b4:	9360      	ld.w      	r3, (r3, 0)
  b6:	934a      	ld.w      	r2, (r3, 0x28)
  b8:	6c08      	or      	r0, r2
  ba:	b30a      	st.w      	r0, (r3, 0x28)
} 
  bc:	07fb      	br      	0xb2	// b2 <ADC12_ConfigInterrupt_CMD+0xe>

000000be <ADC12_Read_IntEnStatus>:
    dat= ADC0->IMR&EnStatus_bit;
  be:	1273      	lrw      	r3, 0	// 208 <ADC12_Configure_VREF_FVR+0x2>
  c0:	9360      	ld.w      	r3, (r3, 0)
  c2:	936b      	ld.w      	r3, (r3, 0x2c)
  c4:	68c0      	and      	r3, r0
    if (dat == EnStatus_bit)								
  c6:	640e      	cmpne      	r3, r0
    return value;
  c8:	6403      	mvcv      	r0
}
  ca:	783c      	rts

000000cc <ADC12_CLK_CMD>:
	if (NewState != DISABLE)
  cc:	3940      	cmpnei      	r1, 0
  ce:	126f      	lrw      	r3, 0	// 208 <ADC12_Configure_VREF_FVR+0x2>
		ADC0->ECR  |= ADC_CLK_CMD;						//ENABLE
  d0:	9340      	ld.w      	r2, (r3, 0)
	if (NewState != DISABLE)
  d2:	0c09      	bf      	0xe4	// e4 <ADC12_CLK_CMD+0x18>
		ADC0->ECR  |= ADC_CLK_CMD;						//ENABLE
  d4:	9260      	ld.w      	r3, (r2, 0)
  d6:	6cc0      	or      	r3, r0
  d8:	b260      	st.w      	r3, (r2, 0)
		while(!(ADC0->PMSR&ADC_CLK_CMD));
  da:	9262      	ld.w      	r3, (r2, 0x8)
  dc:	68c0      	and      	r3, r0
  de:	3b40      	cmpnei      	r3, 0
  e0:	0ffd      	bf      	0xda	// da <ADC12_CLK_CMD+0xe>
}
  e2:	783c      	rts
		ADC0->DCR  |= ADC_CLK_CMD;						//DISABLE
  e4:	9261      	ld.w      	r3, (r2, 0x4)
  e6:	6cc0      	or      	r3, r0
  e8:	b261      	st.w      	r3, (r2, 0x4)
		while(ADC0->PMSR&ADC_CLK_CMD);
  ea:	9262      	ld.w      	r3, (r2, 0x8)
  ec:	68c0      	and      	r3, r0
  ee:	3b40      	cmpnei      	r3, 0
  f0:	0bfd      	bt      	0xea	// ea <ADC12_CLK_CMD+0x1e>
  f2:	07f8      	br      	0xe2	// e2 <ADC12_CLK_CMD+0x16>

000000f4 <ADC12_Software_Reset>:
{
  f4:	14d0      	push      	r15
	ADC12_Control(ADC12_SWRST);
  f6:	3001      	movi      	r0, 1
  f8:	e0000000 	bsr      	0	// 7e <ADC12_Control>
}
  fc:	1490      	pop      	r15

000000fe <ADC12_CMD>:
{
  fe:	14d0      	push      	r15
	if (NewState != DISABLE)
 100:	3840      	cmpnei      	r0, 0
 102:	0c04      	bf      	0x10a	// 10a <ADC12_CMD+0xc>
 104:	e0000000 	bsr      	0	// 8a <ADC12_CMD.part.0>
}
 108:	1490      	pop      	r15
		ADC12_Control(ADC12_ADCDIS);					//ADC12 DISABLE
 10a:	3004      	movi      	r0, 4
 10c:	e0000000 	bsr      	0	// 7e <ADC12_Control>
		while(ADC0->SR&ADC12_ADCENS);
 110:	117e      	lrw      	r3, 0	// 208 <ADC12_Configure_VREF_FVR+0x2>
 112:	3280      	movi      	r2, 128
 114:	9320      	ld.w      	r1, (r3, 0)
 116:	4241      	lsli      	r2, r2, 1
 118:	9168      	ld.w      	r3, (r1, 0x20)
 11a:	68c8      	and      	r3, r2
 11c:	3b40      	cmpnei      	r3, 0
 11e:	0bfd      	bt      	0x118	// 118 <ADC12_CMD+0x1a>
 120:	07f4      	br      	0x108	// 108 <ADC12_CMD+0xa>

00000122 <ADC12_ready_wait>:
//EntryParameter:NONE
//ReturnValue:ADC12 READ FLAG
/*************************************************************/ 
void ADC12_ready_wait(void)  
{
	while(!(ADC0->SR&ADC12_READY));   					// Waiting for ADC0 Ready
 122:	117a      	lrw      	r3, 0	// 208 <ADC12_Configure_VREF_FVR+0x2>
 124:	3202      	movi      	r2, 2
 126:	9320      	ld.w      	r1, (r3, 0)
 128:	9168      	ld.w      	r3, (r1, 0x20)
 12a:	68c8      	and      	r3, r2
 12c:	3b40      	cmpnei      	r3, 0
 12e:	0ffd      	bf      	0x128	// 128 <ADC12_ready_wait+0x6>
}
 130:	783c      	rts

00000132 <ADC12_EOC_wait>:
//EntryParameter:NONE
//ReturnValue:ADC12 EOC
/*************************************************************/ 
void ADC12_EOC_wait(void)
{
	while(!(ADC0->SR & ADC12_EOC));			// EOC wait
 132:	1176      	lrw      	r3, 0	// 208 <ADC12_Configure_VREF_FVR+0x2>
 134:	3201      	movi      	r2, 1
 136:	9320      	ld.w      	r1, (r3, 0)
 138:	9168      	ld.w      	r3, (r1, 0x20)
 13a:	68c8      	and      	r3, r2
 13c:	3b40      	cmpnei      	r3, 0
 13e:	0ffd      	bf      	0x138	// 138 <ADC12_EOC_wait+0x6>
} 
 140:	783c      	rts

00000142 <ADC12_SEQEND_wait>:
//EntryParameter:NONE
//ReturnValue:ADC12 EOC
/*************************************************************/ 
void ADC12_SEQEND_wait(U8_T val)
{
	while(!(ADC0->SR & (0x01ul << (16+val))));			// EOC wait
 142:	200f      	addi      	r0, 16
 144:	1171      	lrw      	r3, 0	// 208 <ADC12_Configure_VREF_FVR+0x2>
 146:	3201      	movi      	r2, 1
 148:	9320      	ld.w      	r1, (r3, 0)
 14a:	7080      	lsl      	r2, r0
 14c:	9168      	ld.w      	r3, (r1, 0x20)
 14e:	68c8      	and      	r3, r2
 150:	3b40      	cmpnei      	r3, 0
 152:	0ffd      	bf      	0x14c	// 14c <ADC12_SEQEND_wait+0xa>
} 
 154:	783c      	rts

00000156 <ADC12_DATA_OUPUT>:
//EntryParameter:NONE
//ReturnValue:ADC12 DR
/*************************************************************/ 
U16_T ADC12_DATA_OUPUT(U16_T Data_index )
{
	return(ADC0->DR[Data_index]);
 156:	203f      	addi      	r0, 64
 158:	116c      	lrw      	r3, 0	// 208 <ADC12_Configure_VREF_FVR+0x2>
 15a:	4002      	lsli      	r0, r0, 2
 15c:	9360      	ld.w      	r3, (r3, 0)
 15e:	600c      	addu      	r0, r3
 160:	9000      	ld.w      	r0, (r0, 0)
 162:	7401      	zexth      	r0, r0
} 
 164:	783c      	rts

00000166 <ADC12_Configure_Mode>:
  //10BIT or 12BIT adc ;
  //ADC12_BIT_SELECTED:ADC12_12BIT/ADC12_10BIT;
  //ADC12_ConverMode:One_shot_mode/Continuous_mode;
  //adc date output=last number of Conversions;
void  ADC12_Configure_Mode(ADC12_10bitor12bit_TypeDef ADC12_BIT_SELECTED  , ADC12_ConverMode_TypeDef  ADC12_ConverMode  , U8_T ADC12_PRI, U8_T ADC12_DIV , U8_T NumConver ) 
{
 166:	14d4      	push      	r4-r7, r15
 168:	d88e0014 	ld.b      	r4, (sp, 0x14)
 16c:	6dcb      	mov      	r7, r2
	ADC0->MR|=ADC12_DIV|((NumConver-1)<<10);
 16e:	2c00      	subi      	r4, 1
 170:	1146      	lrw      	r2, 0	// 208 <ADC12_Configure_VREF_FVR+0x2>
 172:	448a      	lsli      	r4, r4, 10
 174:	92a0      	ld.w      	r5, (r2, 0)
 176:	6cd0      	or      	r3, r4
{
 178:	6d83      	mov      	r6, r0
	ADC0->MR|=ADC12_DIV|((NumConver-1)<<10);
 17a:	9505      	ld.w      	r0, (r5, 0x14)
 17c:	6cc0      	or      	r3, r0
	if(ADC12_ConverMode==One_shot_mode)
 17e:	3940      	cmpnei      	r1, 0
	ADC0->MR|=ADC12_DIV|((NumConver-1)<<10);
 180:	b565      	st.w      	r3, (r5, 0x14)
 182:	6d0b      	mov      	r4, r2
	if(ADC12_ConverMode==One_shot_mode)
 184:	0818      	bt      	0x1b4	// 1b4 <ADC12_Configure_Mode+0x4e>
	{
		ADC0->MR&=~CONTCV;								//one short mode
 186:	9565      	ld.w      	r3, (r5, 0x14)
 188:	4361      	lsli      	r3, r3, 1
 18a:	4b61      	lsri      	r3, r3, 1
		while(ADC0->SR&ADC12_CTCVS);							
 18c:	3280      	movi      	r2, 128
		ADC0->MR&=~CONTCV;								//one short mode
 18e:	b565      	st.w      	r3, (r5, 0x14)
		while(ADC0->SR&ADC12_CTCVS);							
 190:	4242      	lsli      	r2, r2, 2
 192:	9568      	ld.w      	r3, (r5, 0x20)
 194:	68c8      	and      	r3, r2
 196:	3b40      	cmpnei      	r3, 0
 198:	0bfd      	bt      	0x192	// 192 <ADC12_Configure_Mode+0x2c>
 19a:	e0000000 	bsr      	0	// 8a <ADC12_CMD.part.0>
	{
		ADC0->MR|=CONTCV;								//Continuous mode
		while(!(ADC0->SR&ADC12_CTCVS));							
	}
	ADC12_CMD(ENABLE);									//ADC0 enable
	if(ADC12_BIT_SELECTED)
 19e:	3e40      	cmpnei      	r6, 0
 1a0:	0c16      	bf      	0x1cc	// 1cc <ADC12_Configure_Mode+0x66>
	{
		ADC0->CR|=ADC12_10BITor12BIT;
 1a2:	9440      	ld.w      	r2, (r4, 0)
 1a4:	9264      	ld.w      	r3, (r2, 0x10)
 1a6:	3bbf      	bseti      	r3, r3, 31
	}
	else
	{
		ADC0->CR&=~ADC12_10BITor12BIT;
 1a8:	b264      	st.w      	r3, (r2, 0x10)
	}
	ADC0->CR|=ADC12_VREF_VDD | ADC12_FVR_DIS;
 1aa:	9460      	ld.w      	r3, (r4, 0)
 1ac:	9344      	ld.w      	r2, (r3, 0x10)
 1ae:	b344      	st.w      	r2, (r3, 0x10)
	ADC0 ->PRI=ADC12_PRI;
 1b0:	b3fc      	st.w      	r7, (r3, 0x70)
} 
 1b2:	1494      	pop      	r4-r7, r15
	else if(ADC12_ConverMode==Continuous_mode)
 1b4:	3941      	cmpnei      	r1, 1
 1b6:	0bf2      	bt      	0x19a	// 19a <ADC12_Configure_Mode+0x34>
		ADC0->MR|=CONTCV;								//Continuous mode
 1b8:	9565      	ld.w      	r3, (r5, 0x14)
 1ba:	3bbf      	bseti      	r3, r3, 31
		while(!(ADC0->SR&ADC12_CTCVS));							
 1bc:	3280      	movi      	r2, 128
		ADC0->MR|=CONTCV;								//Continuous mode
 1be:	b565      	st.w      	r3, (r5, 0x14)
		while(!(ADC0->SR&ADC12_CTCVS));							
 1c0:	4242      	lsli      	r2, r2, 2
 1c2:	9568      	ld.w      	r3, (r5, 0x20)
 1c4:	68c8      	and      	r3, r2
 1c6:	3b40      	cmpnei      	r3, 0
 1c8:	0ffd      	bf      	0x1c2	// 1c2 <ADC12_Configure_Mode+0x5c>
 1ca:	07e8      	br      	0x19a	// 19a <ADC12_Configure_Mode+0x34>
		ADC0->CR&=~ADC12_10BITor12BIT;
 1cc:	9440      	ld.w      	r2, (r4, 0)
 1ce:	9264      	ld.w      	r3, (r2, 0x10)
 1d0:	4361      	lsli      	r3, r3, 1
 1d2:	4b61      	lsri      	r3, r3, 1
 1d4:	07ea      	br      	0x1a8	// 1a8 <ADC12_Configure_Mode+0x42>

000001d6 <ADC12_TRGSRC_Configure>:
//TRGSRC_Data:ADC_TRG_None/ADC_TRG_SW /ADC_TRG_TC1/ADC_TRG_EPWM/ADC_TRG_CMP /ADC_TRG_EXRE/ADC_TRG_EXFE/ADC_TRG_EXRFE	
//ADC_Channel:0~15
//ReturnValue:NONE
/*************************************************************/ 
void ADC12_TRGSRC_Configure(ADC12_TRGSRC_TypeDef TRGSRC_Data,U8_T ADC_Channel)
{
 1d6:	104d      	lrw      	r2, 0	// 208 <ADC12_Configure_VREF_FVR+0x2>
 1d8:	4162      	lsli      	r3, r1, 2
 1da:	9220      	ld.w      	r1, (r2, 0)
 1dc:	604c      	addu      	r1, r3
	ADC0->SEQ[ADC_Channel] |= TRGSRC_Data;
 1de:	916c      	ld.w      	r3, (r1, 0x30)
 1e0:	6c0c      	or      	r0, r3
 1e2:	b10c      	st.w      	r0, (r1, 0x30)
}
 1e4:	783c      	rts

000001e6 <ADC12_TRGDelay_Configure>:
//Dealy_Time:0~255
//ReturnValue:NONE
/*************************************************************/ 
void ADC12_TRGDelay_Configure(U8_T TRGSRC,U8_T Dealy_Time)
{
	if(TRGSRC<=16)
 1e6:	3810      	cmphsi      	r0, 17
 1e8:	1068      	lrw      	r3, 0	// 208 <ADC12_Configure_VREF_FVR+0x2>
	{
		ADC0->TDL0 = Dealy_Time<<TRGSRC;
 1ea:	9360      	ld.w      	r3, (r3, 0)
	if(TRGSRC<=16)
 1ec:	0804      	bt      	0x1f4	// 1f4 <ADC12_TRGDelay_Configure+0xe>
		ADC0->TDL0 = Dealy_Time<<TRGSRC;
 1ee:	7040      	lsl      	r1, r0
 1f0:	b33d      	st.w      	r1, (r3, 0x74)
	}
	else
	{
		ADC0->TDL1 = (Dealy_Time<<(TRGSRC-32));
	}
}
 1f2:	783c      	rts
		ADC0->TDL1 = (Dealy_Time<<(TRGSRC-32));
 1f4:	281f      	subi      	r0, 32
 1f6:	7040      	lsl      	r1, r0
 1f8:	b33e      	st.w      	r1, (r3, 0x78)
}
 1fa:	07fc      	br      	0x1f2	// 1f2 <ADC12_TRGDelay_Configure+0xc>

000001fc <ADC12_Configure_VREF_VDD>:
//EntryParameter:NONE
//ReturnValue:None
/*************************************************************/ 
void ADC12_Configure_VREF_VDD(void)
{
	ADC0->CR|= ADC12_VREF_VDD | ADC12_FVR_DIS;
 1fc:	1063      	lrw      	r3, 0	// 208 <ADC12_Configure_VREF_FVR+0x2>
 1fe:	9360      	ld.w      	r3, (r3, 0)
 200:	9344      	ld.w      	r2, (r3, 0x10)
 202:	b344      	st.w      	r2, (r3, 0x10)

}
 204:	783c      	rts

00000206 <ADC12_Configure_VREF_FVR>:
//ADC12 VREF slection= Fixed voltage
//EntryParameter:ADC12_FVR_2_048V / ADC12_FVR_4_096V
//ReturnValue:None
/*************************************************************/ 
void ADC12_Configure_VREF_FVR(U32_T FVR_DATA)
{
 206:	0405      	br      	0x210	// 210 <ADC12_Configure_VREF_FVR+0xa>
 208:	00000000 	.long	0x00000000
 20c:	3fffffff 	.long	0x3fffffff
	GPIOD0->CONLR = (GPIOD0->CONLR&0XFFFFFF0F) | 0X00000070;
 210:	1367      	lrw      	r3, 0	// 3ac <ADC12_ConversionChannel_Config+0x11e>
 212:	31f0      	movi      	r1, 240
 214:	9340      	ld.w      	r2, (r3, 0)
 216:	9260      	ld.w      	r3, (r2, 0)
 218:	68c5      	andn      	r3, r1
 21a:	3170      	movi      	r1, 112
 21c:	6cc4      	or      	r3, r1
 21e:	b260      	st.w      	r3, (r2, 0)
	ADC0->CR|=ADC12_VREF_FVR | ADC12_FVR_EN | FVR_DATA;
 220:	1364      	lrw      	r3, 0	// 3b0 <ADC12_ConversionChannel_Config+0x122>
 222:	9340      	ld.w      	r2, (r3, 0)
 224:	9264      	ld.w      	r3, (r2, 0x10)
 226:	3ba8      	bseti      	r3, r3, 8
 228:	3ba9      	bseti      	r3, r3, 9
 22a:	6c0c      	or      	r0, r3
 22c:	b204      	st.w      	r0, (r2, 0x10)
}
 22e:	783c      	rts

00000230 <ADC12_Configure_VREF_EX>:
//EntryParameter:None
//ReturnValue:None
/*************************************************************/ 
void ADC12_Configure_VREF_EX(void)
{
	GPIOD0->CONLR=(GPIOD0->CONLR & 0XFFFFFF0F)|0x00000070; 	
 230:	127f      	lrw      	r3, 0	// 3ac <ADC12_ConversionChannel_Config+0x11e>
 232:	31f0      	movi      	r1, 240
 234:	9340      	ld.w      	r2, (r3, 0)
 236:	9260      	ld.w      	r3, (r2, 0)
 238:	68c5      	andn      	r3, r1
 23a:	3170      	movi      	r1, 112
 23c:	6cc4      	or      	r3, r1
 23e:	b260      	st.w      	r3, (r2, 0)
	ADC0->CR|=ADC12_VREF_FVR | ADC12_FVR_DIS;
 240:	127c      	lrw      	r3, 0	// 3b0 <ADC12_ConversionChannel_Config+0x122>
 242:	9340      	ld.w      	r2, (r3, 0)
 244:	9264      	ld.w      	r3, (r2, 0x10)
 246:	3ba8      	bseti      	r3, r3, 8
 248:	b264      	st.w      	r3, (r2, 0x10)
}
 24a:	783c      	rts

0000024c <ADC12_CompareFunction_set>:
  //ADC will generate a CMPxH/CMPxL interrupt when result of this number of conversion is higher/lower than data set in ADC_CMPx register.
  //ConverNum_CM1Number of Conversions for Compare Function
  //ADC will generate a CMP1H/CMP1L interrupt when result of this number of conversion is greater/less than data set in ADC_CMP1 register.
  
void ADC12_CompareFunction_set(U8_T ConverNum_CM0 , U8_T ConverNum_CM1 , U16_T CMP0_data , U16_T CMP1_data ) 
{
 24c:	14c2      	push      	r4-r5
	ADC0->MR|=((ConverNum_CM0-0)<<16)|((ConverNum_CM1-0)<<22);
 24e:	1299      	lrw      	r4, 0	// 3b0 <ADC12_ConversionChannel_Config+0x122>
 250:	4136      	lsli      	r1, r1, 22
 252:	9480      	ld.w      	r4, (r4, 0)
 254:	4010      	lsli      	r0, r0, 16
 256:	94a5      	ld.w      	r5, (r4, 0x14)
 258:	6c04      	or      	r0, r1
 25a:	6c14      	or      	r0, r5
 25c:	b405      	st.w      	r0, (r4, 0x14)
	ADC0->CMP0=CMP0_data;
 25e:	24ff      	addi      	r4, 256
 260:	b450      	st.w      	r2, (r4, 0x40)
	ADC0->CMP1=CMP1_data;
 262:	b471      	st.w      	r3, (r4, 0x44)
}
 264:	1482      	pop      	r4-r5

00000266 <ADC12_Compare_statue>:
//NBRCMPX_L_TypeDef:NBRCMPX_L_TypeDef,NBRCMPX_H_TypeDef
//ReturnValue:ADC12 Compare result flag
/*************************************************************/ 
  //output statue:ADC-SR(ADC12_CMP0H/ADC12_CMP0L/ADC12_CMP1H/ADC12_CMP1L)
U8_T ADC12_Compare_statue(ADC12_NBRCMPx_TypeDef ADC12_NBRCMPx, ADC12_NBRCMPx_HorL_TypeDef ADC12_NBRCMPx_HorL)
{
 266:	1273      	lrw      	r3, 0	// 3b0 <ADC12_ConversionChannel_Config+0x122>
	if(ADC12_NBRCMPx==NBRCMP0_TypeDef)
 268:	3840      	cmpnei      	r0, 0
	{
		if(ADC12_NBRCMPx_HorL==NBRCMPX_L_TypeDef)
		{
			return((ADC0->SR)&ADC12_CMP0L);
 26a:	9360      	ld.w      	r3, (r3, 0)
 26c:	9308      	ld.w      	r0, (r3, 0x20)
	if(ADC12_NBRCMPx==NBRCMP0_TypeDef)
 26e:	0808      	bt      	0x27e	// 27e <ADC12_Compare_statue+0x18>
		if(ADC12_NBRCMPx_HorL==NBRCMPX_L_TypeDef)
 270:	3940      	cmpnei      	r1, 0
 272:	0804      	bt      	0x27a	// 27a <ADC12_Compare_statue+0x14>
			return((ADC0->SR)&ADC12_CMP0L);
 274:	3320      	movi      	r3, 32
		{
			return((ADC0->SR)&ADC12_CMP1L);
		}
		else
		{
			return((ADC0->SR)&ADC12_CMP1H);
 276:	680c      	and      	r0, r3
 278:	0407      	br      	0x286	// 286 <ADC12_Compare_statue+0x20>
			return((ADC0->SR)&ADC12_CMP0H);
 27a:	3310      	movi      	r3, 16
 27c:	07fd      	br      	0x276	// 276 <ADC12_Compare_statue+0x10>
		if(ADC12_NBRCMPx_HorL==NBRCMPX_L_TypeDef)
 27e:	3940      	cmpnei      	r1, 0
 280:	0805      	bt      	0x28a	// 28a <ADC12_Compare_statue+0x24>
			return((ADC0->SR)&ADC12_CMP1L);
 282:	337f      	movi      	r3, 127
 284:	680d      	andn      	r0, r3
			return((ADC0->SR)&ADC12_CMP1H);
 286:	7400      	zextb      	r0, r0
		}
	}
}
 288:	783c      	rts
			return((ADC0->SR)&ADC12_CMP1H);
 28a:	3340      	movi      	r3, 64
 28c:	07f5      	br      	0x276	// 276 <ADC12_Compare_statue+0x10>

0000028e <ADC12_ConversionChannel_Config>:
//ADC12_ADCINX:ADC12_ADCIN0~ADC12_ADCIN17,ADC12_FVR,ADC12_DIV4_VDD,ADC12_VSS
//ReturnValue:NONE
/*************************************************************/ 
void ADC12_ConversionChannel_Config(ADC12_InputSet_TypeDef ADC12_ADCINX, ADC12_Sampling_TypeDef ADC12_Sample_SELECTED,
						ADC12_CV_RepeatNum_TypeDef CV_RepeatTime, ADC12_Control_TypeDef AVG_Set, U8_T SEQx)
{
 28e:	14d4      	push      	r4-r7, r15
 290:	1422      	subi      	sp, sp, 8
 292:	b820      	st.w      	r1, (sp, 0)
	switch(ADC12_ADCINX)
 294:	3811      	cmphsi      	r0, 18
{
 296:	d82e001c 	ld.b      	r1, (sp, 0x1c)
 29a:	6d83      	mov      	r6, r0
 29c:	b821      	st.w      	r1, (sp, 0x4)
	switch(ADC12_ADCINX)
 29e:	0828      	bt      	0x2ee	// 2ee <ADC12_ConversionChannel_Config+0x60>
 2a0:	1225      	lrw      	r1, 0	// 3b4 <ADC12_ConversionChannel_Config+0x126>
 2a2:	12a6      	lrw      	r5, 0	// 3b8 <ADC12_ConversionChannel_Config+0x12a>
 2a4:	1286      	lrw      	r4, 0	// 3bc <ADC12_ConversionChannel_Config+0x12e>
 2a6:	e0000000 	bsr      	0	// 0 <___gnu_csky_case_uhi>
 2aa:	0012      	.short	0x0012
 2ac:	00430033 	.long	0x00430033
 2b0:	005f0053 	.long	0x005f0053
 2b4:	00760068 	.long	0x00760068
 2b8:	0095008b 	.long	0x0095008b
 2bc:	00ae009f 	.long	0x00ae009f
 2c0:	00cd00bd 	.long	0x00cd00bd
 2c4:	00dd00d5 	.long	0x00dd00d5
 2c8:	00ed00e4 	.long	0x00ed00e4
 2cc:	00f7      	.short	0x00f7
	{
		case 0:	
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC0 PA1.4
 2ce:	9120      	ld.w      	r1, (r1, 0)
 2d0:	9100      	ld.w      	r0, (r1, 0)
 2d2:	b100      	st.w      	r0, (r1, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF)  | 0x00000000;	
 2d4:	9101      	ld.w      	r0, (r1, 0x4)
 2d6:	b101      	st.w      	r0, (r1, 0x4)
			GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF)  | 0x00000000;
 2d8:	9520      	ld.w      	r1, (r5, 0)
 2da:	9100      	ld.w      	r0, (r1, 0)
 2dc:	b100      	st.w      	r0, (r1, 0)
			GPIOA1->CONLR = (GPIOA1->CONLR&0XFFF0FFFF)  | 0x000A0000;							
 2de:	9400      	ld.w      	r0, (r4, 0)
 2e0:	34f0      	movi      	r4, 240
 2e2:	9020      	ld.w      	r1, (r0, 0)
 2e4:	448c      	lsli      	r4, r4, 12
 2e6:	6851      	andn      	r1, r4
 2e8:	39b1      	bseti      	r1, r1, 17
 2ea:	39b3      	bseti      	r1, r1, 19
			break;
		case 1:
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC1 PA1.5
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF)  | 0x00000000;	
			GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF)  | 0x00000000;
			GPIOA1->CONLR = (GPIOA1->CONLR&0XFF0FFFFF)  | 0x00A00000;							
 2ec:	b020      	st.w      	r1, (r0, 0)
 2ee:	9821      	ld.w      	r1, (sp, 0x4)
 2f0:	4122      	lsli      	r1, r1, 2
 2f2:	1110      	lrw      	r0, 0	// 3b0 <ADC12_ConversionChannel_Config+0x122>
		case 0x1Cul: break;
		case 0x1Dul: break;
		case 0x1Eul: break;
	}
	ADC0->SEQ[SEQx] = ADC0->SEQ[SEQx] & 0;
	ADC0->SEQ[SEQx] = ADC0->SEQ[SEQx] | ADC12_ADCINX | ADC12_Sample_SELECTED | CV_RepeatTime | AVG_Set;
 2f4:	6c8c      	or      	r2, r3
 2f6:	9000      	ld.w      	r0, (r0, 0)
 2f8:	6004      	addu      	r0, r1
	ADC0->SEQ[SEQx] = ADC0->SEQ[SEQx] & 0;
 2fa:	902c      	ld.w      	r1, (r0, 0x30)
	ADC0->SEQ[SEQx] = ADC0->SEQ[SEQx] | ADC12_ADCINX | ADC12_Sample_SELECTED | CV_RepeatTime | AVG_Set;
 2fc:	9860      	ld.w      	r3, (sp, 0)
	ADC0->SEQ[SEQx] = ADC0->SEQ[SEQx] & 0;
 2fe:	3100      	movi      	r1, 0
 300:	b02c      	st.w      	r1, (r0, 0x30)
	ADC0->SEQ[SEQx] = ADC0->SEQ[SEQx] | ADC12_ADCINX | ADC12_Sample_SELECTED | CV_RepeatTime | AVG_Set;
 302:	6c8c      	or      	r2, r3
 304:	908c      	ld.w      	r4, (r0, 0x30)
 306:	6d88      	or      	r6, r2
 308:	6d90      	or      	r6, r4
 30a:	b0cc      	st.w      	r6, (r0, 0x30)
}
 30c:	1402      	addi      	sp, sp, 8
 30e:	1494      	pop      	r4-r7, r15
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC1 PA1.5
 310:	9120      	ld.w      	r1, (r1, 0)
 312:	9100      	ld.w      	r0, (r1, 0)
 314:	b100      	st.w      	r0, (r1, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF)  | 0x00000000;	
 316:	9101      	ld.w      	r0, (r1, 0x4)
 318:	b101      	st.w      	r0, (r1, 0x4)
			GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF)  | 0x00000000;
 31a:	9520      	ld.w      	r1, (r5, 0)
 31c:	9100      	ld.w      	r0, (r1, 0)
 31e:	b100      	st.w      	r0, (r1, 0)
			GPIOA1->CONLR = (GPIOA1->CONLR&0XFF0FFFFF)  | 0x00A00000;							
 320:	9400      	ld.w      	r0, (r4, 0)
 322:	34f0      	movi      	r4, 240
 324:	9020      	ld.w      	r1, (r0, 0)
 326:	4490      	lsli      	r4, r4, 16
 328:	6851      	andn      	r1, r4
 32a:	39b5      	bseti      	r1, r1, 21
 32c:	39b7      	bseti      	r1, r1, 23
 32e:	07df      	br      	0x2ec	// 2ec <ADC12_ConversionChannel_Config+0x5e>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC2 PB0.0
 330:	9120      	ld.w      	r1, (r1, 0)
 332:	9100      	ld.w      	r0, (r1, 0)
 334:	b100      	st.w      	r0, (r1, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF)  | 0x00000000;	
 336:	9101      	ld.w      	r0, (r1, 0x4)
 338:	b101      	st.w      	r0, (r1, 0x4)
			GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0)  | 0x0000000A;
 33a:	9500      	ld.w      	r0, (r5, 0)
 33c:	9020      	ld.w      	r1, (r0, 0)
 33e:	350f      	movi      	r5, 15
 340:	6855      	andn      	r1, r5
 342:	39a1      	bseti      	r1, r1, 1
 344:	39a3      	bseti      	r1, r1, 3
			GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFF0F)  | 0x000000A0;
 346:	b020      	st.w      	r1, (r0, 0)
			GPIOA1->CONLR = (GPIOA1->CONLR&0XFFFFFFFF)  | 0x00000000;			
 348:	9420      	ld.w      	r1, (r4, 0)
 34a:	9100      	ld.w      	r0, (r1, 0)
 34c:	b100      	st.w      	r0, (r1, 0)
			break;
 34e:	07d0      	br      	0x2ee	// 2ee <ADC12_ConversionChannel_Config+0x60>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC3 PB0.1
 350:	9120      	ld.w      	r1, (r1, 0)
 352:	9100      	ld.w      	r0, (r1, 0)
 354:	b100      	st.w      	r0, (r1, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF)  | 0x00000000;	
 356:	9101      	ld.w      	r0, (r1, 0x4)
 358:	b101      	st.w      	r0, (r1, 0x4)
			GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFF0F)  | 0x000000A0;
 35a:	9500      	ld.w      	r0, (r5, 0)
 35c:	9020      	ld.w      	r1, (r0, 0)
 35e:	35f0      	movi      	r5, 240
 360:	6855      	andn      	r1, r5
 362:	39a5      	bseti      	r1, r1, 5
 364:	39a7      	bseti      	r1, r1, 7
 366:	07f0      	br      	0x346	// 346 <ADC12_ConversionChannel_Config+0xb8>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFF0)  | 0x0000000A;							//ADC4 PA0.0
 368:	9100      	ld.w      	r0, (r1, 0)
 36a:	9020      	ld.w      	r1, (r0, 0)
 36c:	370f      	movi      	r7, 15
 36e:	685d      	andn      	r1, r7
 370:	39a1      	bseti      	r1, r1, 1
 372:	39a3      	bseti      	r1, r1, 3
			GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF)  | 0xA0000000;							//ADC14 PA0.7
 374:	b020      	st.w      	r1, (r0, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF)  | 0x00000000;	
 376:	9021      	ld.w      	r1, (r0, 0x4)
 378:	040a      	br      	0x38c	// 38c <ADC12_ConversionChannel_Config+0xfe>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC5 PA0.11
 37a:	9100      	ld.w      	r0, (r1, 0)
 37c:	9020      	ld.w      	r1, (r0, 0)
 37e:	b020      	st.w      	r1, (r0, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFF0FFF)  | 0x0000A000;	
 380:	37f0      	movi      	r7, 240
 382:	9021      	ld.w      	r1, (r0, 0x4)
 384:	47e8      	lsli      	r7, r7, 8
 386:	685d      	andn      	r1, r7
 388:	39ad      	bseti      	r1, r1, 13
 38a:	39af      	bseti      	r1, r1, 15
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0)  | 0x0000000A;	
 38c:	b021      	st.w      	r1, (r0, 0x4)
			GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF)  | 0x00000000;
 38e:	9520      	ld.w      	r1, (r5, 0)
 390:	9100      	ld.w      	r0, (r1, 0)
 392:	b100      	st.w      	r0, (r1, 0)
 394:	07da      	br      	0x348	// 348 <ADC12_ConversionChannel_Config+0xba>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC6 PA0.12
 396:	9100      	ld.w      	r0, (r1, 0)
 398:	9020      	ld.w      	r1, (r0, 0)
 39a:	b020      	st.w      	r1, (r0, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFF0FFFF)  | 0x000A0000;	
 39c:	37f0      	movi      	r7, 240
 39e:	9021      	ld.w      	r1, (r0, 0x4)
 3a0:	47ec      	lsli      	r7, r7, 12
 3a2:	685d      	andn      	r1, r7
 3a4:	39b1      	bseti      	r1, r1, 17
 3a6:	39b3      	bseti      	r1, r1, 19
 3a8:	07f2      	br      	0x38c	// 38c <ADC12_ConversionChannel_Config+0xfe>
	...
 3be:	0000      	.short	0x0000
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC7 PA0.13
 3c0:	9100      	ld.w      	r0, (r1, 0)
 3c2:	9020      	ld.w      	r1, (r0, 0)
 3c4:	b020      	st.w      	r1, (r0, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF)  | 0x00A00000;	
 3c6:	37f0      	movi      	r7, 240
 3c8:	9021      	ld.w      	r1, (r0, 0x4)
 3ca:	47f0      	lsli      	r7, r7, 16
 3cc:	685d      	andn      	r1, r7
 3ce:	39b5      	bseti      	r1, r1, 21
 3d0:	39b7      	bseti      	r1, r1, 23
 3d2:	07dd      	br      	0x38c	// 38c <ADC12_ConversionChannel_Config+0xfe>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC8 PA0.14
 3d4:	9100      	ld.w      	r0, (r1, 0)
 3d6:	9020      	ld.w      	r1, (r0, 0)
 3d8:	b020      	st.w      	r1, (r0, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XF0FFFFFF)  | 0x0A000000;	
 3da:	37f0      	movi      	r7, 240
 3dc:	9021      	ld.w      	r1, (r0, 0x4)
 3de:	47f4      	lsli      	r7, r7, 20
 3e0:	685d      	andn      	r1, r7
 3e2:	39b9      	bseti      	r1, r1, 25
 3e4:	39bb      	bseti      	r1, r1, 27
 3e6:	07d3      	br      	0x38c	// 38c <ADC12_ConversionChannel_Config+0xfe>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC9 PA1.0
 3e8:	9120      	ld.w      	r1, (r1, 0)
 3ea:	9100      	ld.w      	r0, (r1, 0)
 3ec:	b100      	st.w      	r0, (r1, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF)  | 0x00000000;	
 3ee:	9101      	ld.w      	r0, (r1, 0x4)
 3f0:	b101      	st.w      	r0, (r1, 0x4)
			GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF)  | 0x00000000;
 3f2:	9520      	ld.w      	r1, (r5, 0)
 3f4:	9100      	ld.w      	r0, (r1, 0)
 3f6:	b100      	st.w      	r0, (r1, 0)
			GPIOA1->CONLR = (GPIOA1->CONLR&0XFFFFFFF0)  | 0x0000000A;	
 3f8:	9400      	ld.w      	r0, (r4, 0)
 3fa:	9020      	ld.w      	r1, (r0, 0)
 3fc:	340f      	movi      	r4, 15
 3fe:	6851      	andn      	r1, r4
 400:	39a1      	bseti      	r1, r1, 1
 402:	39a3      	bseti      	r1, r1, 3
 404:	0774      	br      	0x2ec	// 2ec <ADC12_ConversionChannel_Config+0x5e>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC10 PA1.1
 406:	9120      	ld.w      	r1, (r1, 0)
 408:	9100      	ld.w      	r0, (r1, 0)
 40a:	b100      	st.w      	r0, (r1, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF)  | 0x00000000;	
 40c:	9101      	ld.w      	r0, (r1, 0x4)
 40e:	b101      	st.w      	r0, (r1, 0x4)
			GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF)  | 0x00000000;
 410:	9520      	ld.w      	r1, (r5, 0)
 412:	9100      	ld.w      	r0, (r1, 0)
 414:	b100      	st.w      	r0, (r1, 0)
			GPIOA1->CONLR = (GPIOA1->CONLR&0XFFFFFF0F)  | 0x000000A0;	
 416:	9400      	ld.w      	r0, (r4, 0)
 418:	9020      	ld.w      	r1, (r0, 0)
 41a:	34f0      	movi      	r4, 240
 41c:	6851      	andn      	r1, r4
 41e:	39a5      	bseti      	r1, r1, 5
 420:	39a7      	bseti      	r1, r1, 7
 422:	0765      	br      	0x2ec	// 2ec <ADC12_ConversionChannel_Config+0x5e>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC11 PA1.3
 424:	9120      	ld.w      	r1, (r1, 0)
 426:	9100      	ld.w      	r0, (r1, 0)
 428:	b100      	st.w      	r0, (r1, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF)  | 0x00000000;	
 42a:	9101      	ld.w      	r0, (r1, 0x4)
 42c:	b101      	st.w      	r0, (r1, 0x4)
			GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF)  | 0x00000000;
 42e:	9520      	ld.w      	r1, (r5, 0)
 430:	9100      	ld.w      	r0, (r1, 0)
 432:	b100      	st.w      	r0, (r1, 0)
			GPIOA1->CONLR = (GPIOA1->CONLR&0XFFFF0FFF)  | 0x0000A000;			
 434:	9400      	ld.w      	r0, (r4, 0)
 436:	34f0      	movi      	r4, 240
 438:	9020      	ld.w      	r1, (r0, 0)
 43a:	4488      	lsli      	r4, r4, 8
 43c:	6851      	andn      	r1, r4
 43e:	39ad      	bseti      	r1, r1, 13
 440:	39af      	bseti      	r1, r1, 15
 442:	0755      	br      	0x2ec	// 2ec <ADC12_ConversionChannel_Config+0x5e>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFF0FFFFF)  | 0x00A00000;							//ADC12 PA0.5
 444:	9100      	ld.w      	r0, (r1, 0)
 446:	37f0      	movi      	r7, 240
 448:	9020      	ld.w      	r1, (r0, 0)
 44a:	47f0      	lsli      	r7, r7, 16
 44c:	685d      	andn      	r1, r7
 44e:	39b5      	bseti      	r1, r1, 21
 450:	39b7      	bseti      	r1, r1, 23
 452:	0791      	br      	0x374	// 374 <ADC12_ConversionChannel_Config+0xe6>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XF0FFFFFF)  | 0x0A000000;							//ADC13 PA0.6
 454:	9100      	ld.w      	r0, (r1, 0)
 456:	37f0      	movi      	r7, 240
 458:	9020      	ld.w      	r1, (r0, 0)
 45a:	47f4      	lsli      	r7, r7, 20
 45c:	685d      	andn      	r1, r7
 45e:	39b9      	bseti      	r1, r1, 25
 460:	39bb      	bseti      	r1, r1, 27
 462:	0789      	br      	0x374	// 374 <ADC12_ConversionChannel_Config+0xe6>
			GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF)  | 0xA0000000;							//ADC14 PA0.7
 464:	9100      	ld.w      	r0, (r1, 0)
 466:	9020      	ld.w      	r1, (r0, 0)
 468:	4124      	lsli      	r1, r1, 4
 46a:	4924      	lsri      	r1, r1, 4
 46c:	39bd      	bseti      	r1, r1, 29
 46e:	39bf      	bseti      	r1, r1, 31
 470:	0782      	br      	0x374	// 374 <ADC12_ConversionChannel_Config+0xe6>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC15 PA0.8
 472:	9100      	ld.w      	r0, (r1, 0)
 474:	9020      	ld.w      	r1, (r0, 0)
 476:	b020      	st.w      	r1, (r0, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0)  | 0x0000000A;	
 478:	9021      	ld.w      	r1, (r0, 0x4)
 47a:	370f      	movi      	r7, 15
 47c:	685d      	andn      	r1, r7
 47e:	39a1      	bseti      	r1, r1, 1
 480:	39a3      	bseti      	r1, r1, 3
 482:	0785      	br      	0x38c	// 38c <ADC12_ConversionChannel_Config+0xfe>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC16 PA0.9
 484:	9120      	ld.w      	r1, (r1, 0)
 486:	9100      	ld.w      	r0, (r1, 0)
 488:	b100      	st.w      	r0, (r1, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFF0F)  | 0x000000A0;	
 48a:	9101      	ld.w      	r0, (r1, 0x4)
 48c:	37f0      	movi      	r7, 240
 48e:	681d      	andn      	r0, r7
 490:	38a5      	bseti      	r0, r0, 5
 492:	38a7      	bseti      	r0, r0, 7
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFF0FF)  | 0x00000A00;	
 494:	b101      	st.w      	r0, (r1, 0x4)
 496:	077c      	br      	0x38e	// 38e <ADC12_ConversionChannel_Config+0x100>
			GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF)  | 0x00000000;							//ADC17 PA0.10
 498:	9120      	ld.w      	r1, (r1, 0)
 49a:	9100      	ld.w      	r0, (r1, 0)
 49c:	b100      	st.w      	r0, (r1, 0)
			GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFF0FF)  | 0x00000A00;	
 49e:	37f0      	movi      	r7, 240
 4a0:	9101      	ld.w      	r0, (r1, 0x4)
 4a2:	47e4      	lsli      	r7, r7, 4
 4a4:	681d      	andn      	r0, r7
 4a6:	38a9      	bseti      	r0, r0, 9
 4a8:	38ab      	bseti      	r0, r0, 11
 4aa:	07f5      	br      	0x494	// 494 <ADC12_ConversionChannel_Config+0x206>

000004ac <ADC_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void ADC_Int_Enable(void)
{
    ADC0->CSR=0xFFFFFFFF;
 4ac:	1073      	lrw      	r3, 0	// 4f8 <ADC_Test+0x26>
 4ae:	9340      	ld.w      	r2, (r3, 0)
 4b0:	3300      	movi      	r3, 0
 4b2:	2b00      	subi      	r3, 1
 4b4:	b267      	st.w      	r3, (r2, 0x1c)
	INTC_ISER_WRITE(ADC_INT);    
 4b6:	3208      	movi      	r2, 8
 4b8:	1071      	lrw      	r3, 0	// 4fc <ADC_Test+0x2a>
 4ba:	9360      	ld.w      	r3, (r3, 0)
 4bc:	23ff      	addi      	r3, 256
 4be:	b340      	st.w      	r2, (r3, 0)
}
 4c0:	783c      	rts

000004c2 <ADC_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void ADC_Int_Disable(void)
{
    INTC_ICER_WRITE(ADC_INT);    
 4c2:	106f      	lrw      	r3, 0	// 4fc <ADC_Test+0x2a>
 4c4:	32c0      	movi      	r2, 192
 4c6:	9360      	ld.w      	r3, (r3, 0)
 4c8:	4241      	lsli      	r2, r2, 1
 4ca:	60c8      	addu      	r3, r2
 4cc:	3208      	movi      	r2, 8
 4ce:	b340      	st.w      	r2, (r3, 0)
}
 4d0:	783c      	rts

000004d2 <ADC_Test>:

void ADC_Test(void)
{
 4d2:	14d0      	push      	r15
	U8_T i;
	ADC12_ready_wait(); 
 4d4:	e0000000 	bsr      	0	// 122 <ADC12_ready_wait>
	ADC12_Control(ADC12_START);
 4d8:	3008      	movi      	r0, 8
 4da:	e0000000 	bsr      	0	// 7e <ADC12_Control>
	for (i=0;i<3;i++)
	{
	ADC12_SEQEND_wait(i);
 4de:	3000      	movi      	r0, 0
 4e0:	e0000000 	bsr      	0	// 142 <ADC12_SEQEND_wait>
 4e4:	3001      	movi      	r0, 1
 4e6:	e0000000 	bsr      	0	// 142 <ADC12_SEQEND_wait>
 4ea:	3002      	movi      	r0, 2
 4ec:	e0000000 	bsr      	0	// 142 <ADC12_SEQEND_wait>
	//adc_dr[i]=ADC0->DR[i];
	}
	ADC12_Control(ADC12_STOP);
 4f0:	3010      	movi      	r0, 16
 4f2:	e0000000 	bsr      	0	// 7e <ADC12_Control>
}
 4f6:	1490      	pop      	r15
	...
